RED-V Development Guide

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Contributors: bboyho, Englandsaurus
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What is RISC-V?

RISC-V (pronounced “risk-five”) is a free and open instruction set architecture (ISA) developed by the Computer Science Division of the University of California, Berkeley. The RISC-V ISA is designed to provide "a new level of free, extensible software and hardware freedom on architecture." According to the RISC-V Foundation, the key benefits of RISC-V are:

  • "Software architects / firmware engineers / software developers
    • RISC-V is much more than an open ISA, it is also a frozen ISA. The base instructions are frozen and optional extensions which have been approved are also frozen. Because of the stability of the ISA, software development can confidently be applied to RISC-V knowing that your investment will be preserved. Software written for RISC-V will run on all similar RISC-V cores forever. The frozen ISA provides a solid foundation that software managers can depend on to preserve their software investments. Because the RISC-V ISA is open, this translates to hardware engineers having more flexibility over the processor implementation. With this power, software architects can become more influential in the final hardware implementation. They can provide input to hardware designers to make the RISC-V core more software centric.
  • CTOs / Chip designers / System Architects
    • Innovation is the key enabler of RISC-V. Because the ISA is open, it is the equivalent of everyone having a micro architecture license. One can optimize designs for lower power, performance, security, etc. while keeping full compatibility with other designs. Because there is significantly more control over the hardware implementation, all technical recipients of the architecture can make suggestions at a much earlier point than previously was possible. The result is a solution with significantly fewer compromises. RISC-V also supports custom instructions for designs which require particular acceleration or specialty functions.
  • Board designers
    • In addition to the frozen ISA benefits, RISC-V’s open ISA can provide several additional benefits. For example, if engineers are implementing a soft RISC-V core in an FPGA, often the RTL source code is available. Since RISC-V is royalty free this creates significant flexibility to port a RISC-V based design from an FPGA to an ASIC or another FPGA without any software modifications. Designers who are concerned with security from a trust perspective will also appreciate RISC-V. When the RTL source code is available, this enables deep inspection. With the ability to inspect the RTL, one can establish trust."

For more information about RISC-V, head to the RISC-V Foundation website.